Features

The serial configuration devices provide the following features:

 *-, *-, **-, and **-Mbit flash memory devices that serially configure

Stratix® II FPGAs and the Cyclone™ series FPGAs using the active

serial (AS) configuration scheme

 Easy-to-use four-pin interface

 Low cost, low pin count and non-volatile memory

 Low current during configuration and near-zero standby mode

current

 3.*-V operation

 Available in *-pin and **-pin small outline integrated circuit (SOIC)

package

 Enables the NiosR processor to access unused flash memory through

AS memory interface

 Re-programmable memory with more than **0,**0 erase/program

cycles

Write protection support for memory sectors using status register

bits

 In-system programming support with SRunner software driver

 Programming support with USB Blaster™ or ByteBlaster™ II

download cables

 Additional programming support with the AlteraR Programming

Unit (APU) and programming hardware from BP Microsystems,

System General, and other vendors

 Software design support with the Altera QuartusR II development

system for Windows-based PCs as well as Sun SPARC station and

HP ***0 Series **0/**0

 Delivered with the memory array erased (all the bits set to 1)

1 Whenever the term “serial configuration device(s)” is used in

this document, it refers to Altera EPCS1, EPCS4, EPCS*6, and

EPCS*4 devices.