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EPM7128STC100-15N-Sell Altera all series ICs
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EPM7128STC100-15N-Sell Altera all series ICs

FOB Price

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50 Piece Minimum Order

Country:

Hong Kong

Model No:

EPM7128STC100-15N

FOB Price:

Get Latest Price

Place of Origin:

UNITED STATES

Price for Minimum Order:

-

Minimum Order Quantity:

50 Piece

Packaging Detail:

Original packing(pack in tube, box)

Delivery Time:

IN STOCK, SHIP WITHIN 1 DAY

Supplying Ability:

5000 Piece per Month

Payment Type:

T/T, L/C, D/A, D/P, Western Union, Money Gram, PayPal, Other

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Free Member

Contact Person Mr. Eric

RM 906, WORKINGBERG COMM BLDG, 41-47 MARBLE RD, HONGKONG, HONGKONG

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Product Specification

  • Manufacturer part number:EPM7128STC100-15N
  • distributor:Excellent Integrated System LIMITED
  • Lead Time(Delivery Time):IN STOCK, SHIP WITHIN 1 DAY
  • Condition:NEW & UNUSED, ORIGINAL FACTORY PACKING
  • UNIT PRICE:EMAIL US: sales@eis-ic.com

Product Description

The EPM***8STC*****5N is a high-density, high-performance PLD. It is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based EPM***8STC*****5N provides **0 to 5,**0 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to **5.4 MHz.


Parametrics

EPM***8STC*****5N absolute maximum ratings: (1)VCC, Supply voltage With respect to ground: –2.0 to 7.0 V; (2)VI, DC voltage: –2.0 to 7.0 V; (3)IOUT, DC output current, per pin: –*5 to *5 mA; (4)TSTG, Storage temperature No bias: –*5 to **0℃; (5)TAMB, Ambient temperature Under bias: –*5 to **5℃; (6)TJ, Junction temperature Ceramic packages, under bias: **0℃; (7)PQFP and RQFP packages, under bias: **5℃.


Features

EPM***8STC*****5N features: (1)High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX architecture; (2)5.*-V in-system programmability (ISP) through the built-in IEEE Std. ***9.1 Joint Test Action Group (JTAG) interface available in MAX ***0S devices, ISP circuitry compatible with IEEE Std. ***2; (3)Includes 5.*-V MAX ***0 devices and 5.*-V ISP-based MAX ***0S devices; (4)Built-in JTAG boundary-scan test (BST) circuitry in MAX ***0S devices with **8 or more macrocells; (5)Complete EPLD family with logic densities ranging from **0 to 5,**0 usable gates (see Tables 1 and 2); (6)*-ns pin-to-pin logic delays with up to **5.*-MHz counter frequencies (including interconnect); (7)PCI-compliant devices available.


Diagrams

 


Datasheet

Country: Hong Kong
Model No: EPM7128STC100-15N
FOB Price: Get Latest Price
Place of Origin: UNITED STATES
Price for Minimum Order: -
Minimum Order Quantity: 50 Piece
Packaging Detail: Original packing(pack in tube, box)
Delivery Time: IN STOCK, SHIP WITHIN 1 DAY
Supplying Ability: 5000 Piece per Month
Payment Type: T/T, L/C, D/A, D/P, Western Union, Money Gram, PayPal, Other
Product Group : Integrated Circuit(ICs)

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Mr. Eric < Excellent Integrated System LIMITED (EIS) >

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